[Contents] [Index] [Help] [Retrace] [Browse <] [Browse >]

The serial input data-receive register is 16 bits wide.  It contains the 8
or 9 bit input data and status bits.

The data is received, one bit at a time, into an internal
serial-to-parallel  shift register .  When the proper number of bit times
have elapsed, the contents of this register are transferred to the serial
data read register (SERDATR) shown in Table 8-10, and you are signaled
that there is data ready for you.

Immediately after the transfer of data takes place, the
 receive shift register  again becomes ready to accept new data. After
receiving the receiver-full interrupt, you will have up to one full
character-receive time (8 to 10 bit times) to accept the data and clear
the interrupt. If the interrupt is not cleared in time, the OVERRUN bit is

Table 8-9 shows the definitions of the various bit positions within

               Table 8-9: SERDATR /  ADKCON  Registers


   Number  Name    Function
   ------  ----    --------
   15      OVRUN    OVERRUN
                    (Mirror -- also appears in the interrupt request
                    register.) Indicates that another byte of data was
                    received before the previous byte was picked up by the
                    processor.  To prevent this condition, it is necessary
                    to reset INTF_RBF (bit 11, receive-buffer-full) in
                     INTREQ .

   14      RBF      READ BUFFER FULL
                    (Mirror -- also appears in the interrupt request
                    register.) When this bit is 1, there is data ready to
                    be picked up by the processor.  After reading the
                    contents of this data register, you must reset the
                    INTF_RBF bit in  INTREQ  to prevent an overrun.

                    (Not a mirror -- interrupt occurs when the buffer
                    becomes empty.)  When bit 14 is a 1, the data in the
                    output data register ( SERDAT ) has been transferred to
                    the  serial output shift register , so  SERDAT  is ready
                    to accept another output word.  This is also true when
                    the buffer is empty.

                    This bit is normally used for full-duplex operation.

                    When this bit is a 1, the  output shift register  has
                    completed its task, all data has been transmitted, and
                    the register is now idle.  If you stop writing data
                    into the output register ( SERDAT ), then this bit will
                    become a 1 after both the word currently in the
                     shift register  and the word placed into  SERDAT  have
                    been transmitted.

                    This bit is normally used for half-duplex operation.

   11      RXD      Direct read of  RXD pin  on Paula chip.

   10               Not used at this time.

   9       STP      Stop bit if 9 data bits are specified for receive.

   8       STP      Stop bit if 8 data bits are specified for receive.
           DB8      9th data bit if 9 bits are specified for receive.

   7-0     DB7-DB0  Low 8 data bits of received data.  Data is TRUE (data
                    you read is the same polarity as the data expected).


   Number  Name     Function
   ------  ----     --------
   15      SET/CLR  Allows setting or clearing individual bits.

                    If bit 15 is a 1 specified bits are set.
                    If bit 15 is a 0 specified bits are cleared.

   11      UARTBRK  Force the transmit pin to zero.

[Back to Amiga Developer Docs]