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 Figure 1-1: Block Diagram for the Amiga Computer Family 
 Figure 2-1: Interlaced Bitplane in RAM 
 Figure 3-1: How the Video Display Picture Is Produced 
 Figure 3-2: What Is a Pixel? 
 Figure 3-3: How Bitplanes Select a Color 
 Figure 3-4: Significance of Bitplane Data in Selecting Colors 
 Figure 3-5: Interlacing 
 Figure 3-6: Effect of Interlaced Mode on Edges of Objects 
 Figure 3-7: Memory Organization for a Basic Bitplane 
 Figure 3-8: Combining Bitplanes 
 Figure 3-9: Positioning the On-screen Display 
 Figure 3-10: Data Fetched for the First Line When Modulo = 0 
 Figure 3-11: Data Fetched for the Second Line When Modulo = 0 
 Figure 3-12: A Dual-playfield Display 
 Figure 3-13: How Bitplanes Are Assigned to Dual Playfields 
 Figure 3-14: Memory Picture Larger than the Display 
 Figure 3-15: Data Fetch for the First Line When Modulo = 40 
 Figure 3-16: Data Fetch for the Second Line When Modulo = 40 
 Figure 3-17: Data Layout for First Line -- Right Half of Big Picture 
 Figure 3-18: Data Layout for Second Line -- Right Half of Big Picture 
 Figure 3-19: Display Window Horizontal Starting Position 
 Figure 3-20: Display Window Vertical Starting Position 
 Figure 3-21: Display Window Horizontal Stopping Position 
 Figure 3-22: Display Window Vertical Stopping Position 
 Figure 3-23: Vertical Scrolling 
 Figure 3-24: Horizontal Scrolling 
 Figure 3-25: Memory Picture Larger Than the Display Window 
 Figure 3-26: Data for Line 1 - Horizontal Scrolling 
 Figure 3-27: Data for Line 2 - Horizontal Scrolling 
 Figure 4-1: Defining Sprite On-screen Position 
 Figure 4-2: Position of Sprites 
 Figure 4-3: Shape of Spaceship 
 Figure 4-4: Sprite with Spaceship Shape Defined 
 Figure 4-5: Sprite Color Definition 
 Figure 4-6: Color Register Assignments 
 Figure 4-7: Data Structure Layout 
 Figure 4-8: Sprite Priority 
 Figure 4-9: Typical Example of Sprite Reuse 
 Figure 4-10: Typical Data Structure for Sprite Re-use 
 Figure 4-11: Overlapping Sprites (Not Attached) 
 Figure 4-12: Placing Sprites Next to Each Other 
 Figure 4-13: Sprite Control Circuitry 
 Figure 5-1: Sine Waveform 
 Figure 5-2: Digitized Amplitude Values 
 Figure 5-3: Example Sine Wave 
 Figure 5-4: Waveform with Multiple Cycles 
 Figure 5-5: Frequency Domain Plot of Low-Pass Filter 
 Figure 5-6: Noise-free Output (No Aliasing Distortion) 
 Figure 5-7: Some Aliasing Distortion 
 Figure 5-8: Audio State Diagram 
 Figure 6-1: How Images are Stored in Memory 
 Figure 6-2: BLTxPTR and BLTxMOD calculations 
 Figure 6-3: Blitter Minterm Venn Diagram 
 Figure 6-4: Extracting a Range of Columns 
 Figure 6-5: Use of the FCI Bit - Bit Is a 0 
 Figure 6-6: Use of the FCI Bit - Bit Is a 1 
 Figure 6-7: Single-Point Vertex Example 
 Figure 6-8: Octants for Line Drawing 
 Figure 6-9: DMA Time Slot Allocation 
 Figure 6-10: Normal 68000 Cycle 
 Figure 6-11: Time Slots Used by a Six Bitplane Display 
 Figure 6-12: Time Slots Used by a High Resolution Display 
 Figure 6-13: Blitter Block Diagram 
 Figure 7-1: Inter-Sprite Fixed Priorities 
 Figure 7-2: Analogy for Video Priority 
 Figure 7-3: Sprite/Playfield Priority 
 Figure 7-4: Interrupt Priorities 
 Figure 8-1: Controller Plug and Computer Connector 
 Figure 8-2: Mouse Quadrature 
 Figure 8-3: Joystick to Counter Connections 
 Figure 8-4: Typical Paddle Wiring Diagram 
 Figure 8-5: Effects of Resistance on Charging Rate 
 Figure 8-6: Potentiometer Charging Circuit 
 Figure 8-7: Chinon Write Timing Diagram 
 Figure 8-8: Chinon Access Timing Diagram 
 Figure 8-9: Chinon Read Timing Diagram 
 Figure 8-10: The Amiga 1000 Keyboard 
 Figure 8-11: The Amiga 500/2000/3000 Keyboard 
 Figure 8-12: Starting Appearance of SERDAT and Shift Register 
 Figure 8-13: Ending Appearance of Shift Register 
 Figure D-1: Amiga 3000 Memory Map 
 Figure E-1: Reading Fire Buttons 
 Figure E-2: Pot Counters 
 Figure E-3: Light Pen 
 Figure K-1: Expansion Memory Map 
 Figure K-2: A2000 vs A3000 Bus Termination 
 Figure K-3: Expansion Bus Clocks 
 Figure K-4: Zorro II Bus Arbitration 
 Figure k-5: Basic Zorro III Cycle 
 Figure K-6: Multiple Transfer Cycles 
 Figure K-7: Zorro III Bus Arbitration 
 Figure K-8: Interrupt Vector Cycle 
 Figure K-9: Zorro II Within Zorro III 
 Figure K-10: Read Cycle Timing 
 Figure K-11: Write Cycle Timing 
 Figure K-12: Multiple Transfer Cycle Timing 
 Figure K-13: Quick Interrupt Cycle Timing 
 Figure K-14: Basic Zorro III Pic 
 Figure K-15: Pic with ISA Option 
 Figure K-16: Pic with Video Option 
 Figure K-17: Configuration Register Map 

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